Intel® Xeon Phi™ Coprocessor Architecture and Tools (Record no. 43327)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03191nam a22004097a 4500 |
| 001 - CONTROL NUMBER | |
| control field | sulb-eb0021235 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | BD-SySUS |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20160413122135.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 130926s2013 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781430259275 |
| -- | 978-1-4302-5927-5 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/978-1-4302-5927-5 |
| Source of number or code | doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | QA75.5-76.95 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UY |
| Source | bicssc |
| Subject category code | COM014000 |
| Source | bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 004 |
| Edition number | 23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Rahman, Rezaur. |
| Relator term | author. |
| 245 10 - TITLE STATEMENT | |
| Title | Intel® Xeon Phi™ Coprocessor Architecture and Tools |
| Medium | [electronic resource] : |
| Remainder of title | The Guide for Application Developers / |
| Statement of responsibility, etc. | by Rezaur Rahman. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Berkeley, CA : |
| Name of producer, publisher, distributor, manufacturer | Apress : |
| -- | Imprint: Apress, |
| Date of production, publication, distribution, manufacture, or copyright notice | 2013. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | XXI, 232 p. |
| Other physical details | online resource. |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Content type code | txt |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | computer |
| Media type code | c |
| Source | rdamedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Carrier type code | cr |
| Source | rdacarrier |
| 347 ## - DIGITAL FILE CHARACTERISTICS | |
| File type | text file |
| Encoding format | |
| Source | rda |
| 506 0# - RESTRICTIONS ON ACCESS NOTE | |
| Terms governing access | Open Access |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers provides developers a comprehensive introduction and in-depth look at the Intel Xeon Phi coprocessor architecture and the corresponding parallel data structure tools and algorithms used in the various technical computing applications for which it is suitable. It also examines the source code-level optimizations that can be performed to exploit the powerful features of the processor. Xeon Phi is at the heart of world’s fastest commercial supercomputer, which thanks to the massively parallel computing capabilities of Intel Xeon Phi processors coupled with Xeon Phi coprocessors attained 33.86 teraflops of benchmark performance in 2013. Extracting such stellar performance in real-world applications requires a sophisticated understanding of the complex interaction among hardware components, Xeon Phi cores, and the applications running on them. In this book, Rezaur Rahman, an Intel leader in the development of the Xeon Phi coprocessor and the optimization of its applications, presents and details all the features of Xeon Phi core design that are relevant to the practice of application developers, such as its vector units, hardware multithreading, cache hierarchy, and host-to-coprocessor communication channels. Building on this foundation, he shows developers how to solve real-world technical computing problems by selecting, deploying, and optimizing the available algorithms and data structure alternatives matching Xeon Phi’s hardware characteristics. From Rahman’s practical descriptions and extensive code examples, the reader will gain a working knowledge of the Xeon Phi vector instruction set and the Xeon Phi microarchitecture whereby cores execute 512-bit instruction streams in parallel. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer science. |
| Topical term or geographic name as entry element | Computer Science. |
| Topical term or geographic name as entry element | Computer Science, general. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Printed edition: |
| International Standard Book Number | 9781430259268 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="http://dx.doi.org/10.1007/978-1-4302-5927-5">http://dx.doi.org/10.1007/978-1-4302-5927-5</a> |
| 912 ## - | |
| -- | ZDB-2-CWD |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | |
| Koha item type | |
No items available.