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Design, Analysis and Test of Logic Circuits Under Uncertainty (Record no. 48281)

MARC details
000 -LEADER
fixed length control field 03672nam a22005897a 4500
001 - CONTROL NUMBER
control field sulb-eb0026189
003 - CONTROL NUMBER IDENTIFIER
control field BD-SySUS
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20160413122617.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 120921s2013 ne | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9789048196449
-- 978-90-481-9644-9
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/978-90-481-9644-9
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7888.4
072 #7 - SUBJECT CATEGORY CODE
Subject category code TJFC
Source bicssc
Subject category code TEC008010
Source bisacsh
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Krishnaswamy, Smita.
Relator term author.
245 10 - TITLE STATEMENT
Title Design, Analysis and Test of Logic Circuits Under Uncertainty
Medium [electronic resource] /
Statement of responsibility, etc. by Smita Krishnaswamy, Igor L. Markov, John P. Hayes.
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture Dordrecht :
Name of producer, publisher, distributor, manufacturer Springer Netherlands :
-- Imprint: Springer,
Date of production, publication, distribution, manufacture, or copyright notice 2013.
300 ## - PHYSICAL DESCRIPTION
Extent XII, 124 p.
Other physical details online resource.
336 ## - CONTENT TYPE
Content type term text
Content type code txt
Source rdacontent
337 ## - MEDIA TYPE
Media type term computer
Media type code c
Source rdamedia
338 ## - CARRIER TYPE
Carrier type term online resource
Carrier type code cr
Source rdacarrier
347 ## - DIGITAL FILE CHARACTERISTICS
File type text file
Encoding format PDF
Source rda
490 1# - SERIES STATEMENT
Series statement Lecture Notes in Electrical Engineering,
International Standard Serial Number 1876-1100 ;
Volume/sequential designation 115
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Introduction -- Probabilistic Transfer Matrices -- Computing with Probabilistic Transfer Matrices -- Testing Logic Circuits for Probabilistic Faults -- Signtaure-based Reliability Analysis -- Design for Robustness -- Summary and Extensions.
520 ## - SUMMARY, ETC.
Summary, etc. Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits.  To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits.  The book describes techniques for:   • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;   • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-level optimizations;   • Logic synthesis for greater resilience against soft errors, which improves reliability using moderate overhead in area and performance;   • Test-generation and test-compaction methods aimed at probabilistic faults in logic circuits that facilitate accurate and efficient post-manufacture measurement of soft-error susceptibility.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
Topical term or geographic name as entry element Computer hardware.
Topical term or geographic name as entry element Arithmetic and logic units, Computer.
Topical term or geographic name as entry element Logic design.
Topical term or geographic name as entry element Computer software
General subdivision Reusability.
Topical term or geographic name as entry element Computer science
General subdivision Mathematics.
Topical term or geographic name as entry element Electronic circuits.
Topical term or geographic name as entry element Engineering.
Topical term or geographic name as entry element Circuits and Systems.
Topical term or geographic name as entry element Arithmetic and Logic Structures.
Topical term or geographic name as entry element Computer Hardware.
Topical term or geographic name as entry element Performance and Reliability.
Topical term or geographic name as entry element Logic Design.
Topical term or geographic name as entry element Symbolic and Algebraic Manipulation.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Markov, Igor L.
Relator term author.
Personal name Hayes, John P.
Relator term author.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Printed edition:
International Standard Book Number 9789048196432
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Lecture Notes in Electrical Engineering,
International Standard Serial Number 1876-1100 ;
Volume number/sequential designation 115
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="http://dx.doi.org/10.1007/978-90-481-9644-9">http://dx.doi.org/10.1007/978-90-481-9644-9</a>
912 ## -
-- ZDB-2-ENG
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Koha item type

No items available.