MARC details
| 000 -LEADER |
|---|
| fixed length control field |
02227nam a22003017a 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
sulbI001725 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
BD-SySUS |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20160629131328.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
160629s2010 enka b 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780521872447 (hardback) |
|
|---|
| International Standard Book Number |
0521872448 (hardback) |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
DLC |
| Transcribing agency |
DLC |
| Modifying agency |
C#P |
| -- |
CDX |
| -- |
BWX |
| -- |
YDXCP |
| -- |
UKM |
| -- |
DLC |
| -- |
BD-SySUS |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395 |
| Edition number |
22 |
| Item number |
BED |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Beerel, Peter A. |
| 9 (RLIN) |
28329 |
| 245 12 - TITLE STATEMENT |
|---|
| Title |
A designer's guide to asynchronous VLSI / |
| Statement of responsibility, etc. |
Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc. |
Cambridge ; |
| -- |
New York : |
| Name of publisher, distributor, etc. |
Cambridge University Press, |
| Date of publication, distribution, etc. |
2010. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xii, 339 p. : |
| Other physical details |
ill. ; |
| Dimensions |
26 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
"Bypass the limitations of synchronous design and create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. The fundamentals of asynchronous design are covered, as is a large variety of design styles, while the emphasis throughout is on practical techniques and real-world applications"--Provided by publisher. |
|
|---|
| Summary, etc. |
"This book provides an introduction to this diverse area of VLSI from a designer's point of view. Our goal is to enable designers to appreciate the many asynchronous design choices that may be readily available in the near future"--Provided by publisher. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Integrated circuits |
| General subdivision |
Very large scale integration |
| -- |
Computer-aided design. |
| 9 (RLIN) |
16984 |
|
|---|
| Topical term or geographic name as entry element |
Integrated circuits |
| General subdivision |
Very large scale integration |
| -- |
Design and construction. |
| 9 (RLIN) |
24419 |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Ozdag, Recep O. |
| 9 (RLIN) |
28330 |
|
|---|
| Personal name |
Ferretti, Marcos. |
| 9 (RLIN) |
28331 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Cover image |
| Uniform Resource Identifier |
<a href="http://assets.cambridge.org/97805218/72447/cover/9780521872447.jpg">http://assets.cambridge.org/97805218/72447/cover/9780521872447.jpg</a> |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |
