TY  - BOOK
AU  - Daněk,Martin
AU  - Kafka,Leoš
AU  - Kohout,Lukáš
AU  - Sýkora,Jaroslav
AU  - Bartosinski,Roman
ED  - SpringerLink (Online service)
TI  - UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs
SN  - 9781461424109
AV  - TK7888.4 
U1  - 621.3815 23
PY  - 2013///
CY  - New York, NY
PB  - Springer New York, Imprint: Springer
KW  - Engineering
KW  - Microprocessors
KW  - Electronics
KW  - Microelectronics
KW  - Electronic circuits
KW  - Circuits and Systems
KW  - Processor Architectures
KW  - Electronics and Microelectronics, Instrumentation
N1  - Introduction -- The LEON3 Processor -- Microthreaded Extensions -- The Basic UTLEON3 Architecture.- UTLEON3 Programming by Example -- UTLEON3 Implementation Details -- Execution Effieciency of the Microthread Pipeline.- Hardware Families of Threads -- I/O and Interrupt Handling in the Microthread Mode -- The IU3 Pipeline -- Excerpts from the LEON3 Instruction Set -- Relevant LEON3 Registers and Address Space Identifiers.- Scheduler Example -- Used Resources -- Tutorial
N2  - This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs.  Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch; Provides VHDL sources for the described processor; Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines; Includes programming by example in the micro-threaded assembly language.    
UR  - http://dx.doi.org/10.1007/978-1-4614-2410-9
ER  -