TY  - BOOK
AU  - Zatt,Bruno
AU  - Shafique,Muhammad
AU  - Bampi,Sergio
AU  - Henkel,Jörg
ED  - SpringerLink (Online service)
TI  - 3D Video Coding for Embedded Devices: Energy Efficient Algorithms and Architectures 
SN  - 9781461467595
AV  - TK7888.4 
U1  - 621.3815 23
PY  - 2013///
CY  - New York, NY
PB  - Springer New York, Imprint: Springer
KW  - Engineering
KW  - Microprocessors
KW  - Electronics
KW  - Microelectronics
KW  - Electronic circuits
KW  - Circuits and Systems
KW  - Electronics and Microelectronics, Instrumentation
KW  - Processor Architectures
N1  - Introduction -- Background and Related Work -- Multiview Video Coding Analysis for Energy and Quality -- Energy-Effiecient Algorithms for Multiview Video Coding -- Energy-Efficient Architectures for Multiview Video Coding -- Results and Comparison -- Conclusion and future Works
N2  - This book shows readers how to develop energy-efficient algorithms and hardware architectures to enable high-definition 3D video coding on resource-constrained embedded devices.  Users of the Multiview Video Coding (MVC) standard face the challenge of exploiting its 3D video-specific coding tools for increasing compression efficiency at the cost of increasing computational complexity and, consequently, the energy consumption.  This book enables readers to reduce the multiview video coding energy consumption through jointly considering the algorithmic and architectural levels.  Coverage includes an introduction to 3D videos and an extensive discussion of the current state-of-the-art of 3D video coding, as well as energy-efficient algorithms for 3D video coding and energy-efficient hardware architecture for 3D video coding.     ·         Discusses challenges related to performance and power in 3D video coding for embedded devices; ·         Describes energy-efficient algorithms for reducing computational complexity at multiple hierarchical levels; ·         Presents energy-efficient hardware architectures along with methods for reducing on-chip and off-chip energy related to both data processing and memory access; ·         Shows how to leverage jointly the algorithm and hardware architecture layers of the system
UR  - http://dx.doi.org/10.1007/978-1-4614-6759-5
ER  -