Finite State Machine Logic Synthesis for Complex Programmable Logic Devices
Czerwinski, Robert.
Finite State Machine Logic Synthesis for Complex Programmable Logic Devices [electronic resource] / by Robert Czerwinski, Dariusz Kania. - XV, 172 p. online resource. - Lecture Notes in Electrical Engineering, 231 1876-1100 ; . - Lecture Notes in Electrical Engineering, 231 .
Introduction -- Definitions and Basic Properties -- Synthesis of FSMs -- State Assignment Algorithms -- Theoretical Background of Technology-Dependent Optimization -- The Algorithm of Area Optimization Based on Graphs of Outputs -- Conclusions -- Output File Format -- Conclusion.
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can also be interpreted as programmable AND-fixed OR structure, well known as PAL-based structure. The question is: what should be done when the number of implicants representing function exceeds the number of product terms available in a logic block. The answer is ... in the book. Logic synthesis and optimization methods dedicated for PAL-based structures are proposed. The methods strive to find the optimum fit for the combinational logic and finite state machines to the structure of the logic device and aim at area and speed optimization. The theoretical background and complete strategies are richly illustrated with examples and figures.
9783642361661
10.1007/978-3-642-36166-1 doi
Engineering.
Logic design.
Engineering design.
Electronic circuits.
Engineering.
Circuits and Systems.
Logic Design.
Engineering Design.
TK7888.4
621.3815
Finite State Machine Logic Synthesis for Complex Programmable Logic Devices [electronic resource] / by Robert Czerwinski, Dariusz Kania. - XV, 172 p. online resource. - Lecture Notes in Electrical Engineering, 231 1876-1100 ; . - Lecture Notes in Electrical Engineering, 231 .
Introduction -- Definitions and Basic Properties -- Synthesis of FSMs -- State Assignment Algorithms -- Theoretical Background of Technology-Dependent Optimization -- The Algorithm of Area Optimization Based on Graphs of Outputs -- Conclusions -- Output File Format -- Conclusion.
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can also be interpreted as programmable AND-fixed OR structure, well known as PAL-based structure. The question is: what should be done when the number of implicants representing function exceeds the number of product terms available in a logic block. The answer is ... in the book. Logic synthesis and optimization methods dedicated for PAL-based structures are proposed. The methods strive to find the optimum fit for the combinational logic and finite state machines to the structure of the logic device and aim at area and speed optimization. The theoretical background and complete strategies are richly illustrated with examples and figures.
9783642361661
10.1007/978-3-642-36166-1 doi
Engineering.
Logic design.
Engineering design.
Electronic circuits.
Engineering.
Circuits and Systems.
Logic Design.
Engineering Design.
TK7888.4
621.3815