Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits [electronic resource] / by Martin Wirnshofer.

1 Introduction -- 2 Sources of Variation -- 3 Related Work -- 4 Adaptive Voltage Scaling by In-situ Delay Monitoring -- 5 Design of In-situ Delay Monitors -- 6 Modeling the AVS Control Loop -- 7 Evaluation of the Pre-Error AVS Approach -- 8 Conclusion -- A Appendix -- A.1 Mathematical Derivation: Path Delay under Local Variations -- A.2 2-D DCT Transform -- References.

Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted “on the fly” by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engineers interested in adaptive techniques for low-power CMOS circuits.